A VLSI Architecture for Enhancing the Fault Tolerance of NoC using Quad-spare Mesh Topology and Dynamic Reconfiguration

In this paper. a VLSI architecture employing router-level redundancy. referred to as a quad-spare mesh. is proposed for fault tolerant NoC designs. This design deals with the problem that a faulty router breaks the communication between healthy PEs. The proposed design significantly improves a system’s reliability and its mean time to failure. Topology reconfiguration and routing algorithm can be performed dynamically. The NoC after reconfiguration is consistent to the original network. which implies that this design is transparent to the upper layers including operating systems and user applications. In the proposed quad-spare mesh. the reliability of an NoC is improved by using spare routers. which are regularly connected to as many original routers as possible. Therefore. the hardware overhead is kept low with a high throughput. This idea on the use of redundancy is not restricted in the 2Dmesh topology. it could also be used in NoCs with other types of topologies and could further be extended to tolerate faulty links. The proposed fault tolerant architecture is therefore scalable and potentially useful in future NoC designs.

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