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We present a non-traditional CMOS inverter composed a junctionless (JL) NMOSFET and an N+ -N–P transistor which with simple process and high integration density in this paper. In the non-traditional CMOS inverter the JL NMOSFET serves as driver and the N–P transistor serves as load. respectively. Based on the measurement date of the N+ -N–P transistor published. we draw the load line of the non-traditional CMOS inverter and we found out that the N–P transistor can be used in the COMS circuit to advance the issues of the conventional CMOS today. Besides. the area reduced more than 46.1 % are also be achieved.
As the semiconductor technology developed continues. the complementary metal-oxide semiconductor (CMOS) logical devices have been used in the digital circuits as well as the very-large-scale integration (VLSI) generally. because of its low static power consumption and good noise margin. Unfortunately. the complicated process. high fabrication cost. and the non-matched mobility are the serious issues of the silicon-based CMOS logical devices. Also. when the device dimensions are scaled-down. the wider width of PMOSFETs appears to be difficult to achieve the high integration density. A number of CMOS studies have been reported to ease the issues mentioned above. including the device fabricated on silicon-oninsulator (SOl) substrate [1]. and on germanium-oninsulator (GeOl) substrate [2]. on III-V materials [3] [4]. or use of stress engineering and three-dimensional (3-D) integration technology [5]. However. the width compensation of PMOSFETs and its complicated processes still exist.
