Articles

A VLSI Architecture for Enhancing the Fault Tolerance of NoC using Quad-spare Mesh Topology and Dynamic Reconfiguration

In this paper. a VLSI architecture employing router-level redundancy. referred to as a quad-spare mesh. is proposed for fault tolerant NoC designs. This design deals with the problem that a faulty router breaks the communication between healthy PEs. The proposed design significantly improves a system’s reliability and its mean time …

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Transformer failure due to circuit breaker induced switching transients applicable to the cement industry

Switching transients associated with circuit breakers have been observed for many years. Recently this phenomenon has been attributed to a significant number of transformer failures involving primary circuit breaker switching. These transformer failures had common contributing factors such as 1) primary vacuum or SF-6 breaker. 2) short cable or bus …

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A Coordinated Design of PSSs and UPFC-based Stabilizer Using Genetic Algorithm

Using a criterion based on the damping ratio. an optimization algorithm was successfully applied to establish the optimal coordination between PSSs and UPFC-based stabilizer using Genetic Algorithm (GA). A multi-objective function was utilized to formulate the problem. whose solution aims to maximize the damping ratios of the electromechanical modes using …

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